UESTION ONE$\backslash$table$[[$Element$,$Parameter,Delay $($ps$)],[$Register clk$-$to$-$Q$,t_{pcq},40],[$Register setup,$t_{\text{s}\text{e}\text{t}\text{u}\text{p}},50],[$Multiplexer$,t_{\text{m}\text{u}\text{x}},30],[$AND$-$OR gate,$t_{\text{A}\text{N}\text{D}-OR},20],[$ALU$,t_{\text{A}\text{L}\text{U}},120],[$Decoder $($control unit$),t_{\text{d}\text{e}\text{c}},25],[$Extend unit,$t_{\text{e}\text{x}\text{t}},35],[$Memory read,$t_{\text{m}\text{e}\text{m}},200],[$Register file read,$t_{\text{R}\text{F}\text{r}\text{e}\text{a}\text{d}},100],[$Register file setup,$t_{\text{R}\text{F}\text{s}\text{e}\text{t}\text{u}\text{p}},60]]$

$($a$)$ Which unit should she work on to obtain the greatest speedup of the overall processor? Explain why $[5]$

$($b$)$ What would the cycle time of the improved machine be$?[2]$

$($c$)$ Consider how this change might affect an application scenario such as a real$-$time audio processing system How would the altered component impact the system's overall performance in this context? $[5]$

Assume a MIPS processor running a health monitoring application with a clock rate of $2GHz.$ If the

application executes $13$ billion instructions with an average CPI of $1\mathrm{.}5,$ calculate the execution time. Then,

propose optimizations in line with Moore's Law to improve performance. $5,5$

Analyze the following $C++$ code snippet, where A and $B$ are arrays of $64-$bit integers, while $C$ and i are

$64-$bit integer variables. Data values and their addresses for $A,3000$ for $B,5000$ for $C,$ and $7000$ for

i are stored in memory, except during operations. Note that register values are not retained across loop

iterations.

$($a$)$ Write machine code $($in hexadecimal format$)$ equivalent for MIPS. $[10]$

$($b$)$ How many instructions are required dynamically? $[5]$

$($c$)$ How many memory$-$data references will be executed? $[2]$

$($d$)$ What is the code size in bytes? $[3]$

UESTION TWO

Discuss how to extend the MIPS ISA and microarchitecture $($datapath and control unit$)$ to include lwpreinc,

which performs preindexing. lwpreinc $rd,$imm$(rs)$ is equivalent to the following two instructions: $[8]$

Imagine you are collaborating with a friend who is an expert in circuit design. They propose to optimize

a component in a single$-$cycle MIPS processor, reducing its delay by half. Given the delays of the various

components listed below, address the subsequent questions.