uploud the file and provide the final answer

Q2 Verilog Test Benches 4 Points Write a Verilog test bench file for the module in Question 1 using the following test patterns: - Initially, apply AB=00 - After 7 time units (counting from initial time), apply AB=01 - After 14 time units (counting from initial time), apply AB=11 - Stop simulation at time =25 time units. Use the box below to type your Verilog test bench module: Enter your answer here Use the upload button below to upload the waveform of your test bench (in PDF): D Please select file(s)