Use Figures Q2_1, 2, 3 and Tables Q2_1, 2, 3, 4, as necessary, to solve the following questions: (a) Design the register address logic in the pipelined CISC CPU by using information given in the register fields of the Table shown below plus multiple-bit multiplexers, AND gates, OR gates, and inverters. [10 Marks] (b) Write microcode in the table shown below for the execution part of the following CISC instruction that is specified by register transfer statements: Add with carry (AWC): R[DR] R[SA] +R[SB] + C Give both a register transfer description and binary or hexadecimal representations. [15 Marks] 39 40 31 25 30 29 16 2 = 12 22 13 24 23 21 20 19 15 14 PL D 0 1 Action Address MI R DN Use Figures Q2_1, 2, 3 and Tables Q2_1, 2, 3, 4, as necessary, to solve the following questions: (a) Design the register address logic in the pipelined CISC CPU by using information given in the register fields of the Table shown below plus multiple-bit multiplexers, AND gates, OR gates, and inverters. [10 Marks] (b) Write microcode in the table shown below for the execution part of the following CISC instruction that is specified by register transfer statements: Add with carry (AWC): R[DR] R[SA] +R[SB] + C Give both a register transfer description and binary or hexadecimal representations. [15 Marks] 39 40 31 25 30 29 16 2 = 12 22 13 24 23 21 20 19 15 14 PL D 0 1 Action Address MI R DN