Use manufacturers data sheets and your textbook to help you complete the following. If you are having a problem understanding the data sheet from one manufacturer, try another manufacturer. The amount of information and the descriptions often vary from one manufacturer to another.

create the schematic(s).

Part I

1. Use the 74HC164/74HCT164 shift register to complete the SRG8 Data Input Register section in Figure 8-31 of your textbook (also in the slide show).
2. Show all inputs and outputs for the IC including pin numbers. Include the other sections of the block diagram to clearly indicate the connections to and from the 74HC164. You do not need to draw complete schematics for the other sections. Include them in your schematic as they are given; only provide the completed circuit for the 74HC164. (7 marks mark for each correct input and output.)

Part II

1. Using the 74HC165/74HCT165 shift register, design a circuit to load the binary value 10110111 into the shift register at power up and then shift the bits out serially. Binary zeros should be shifted out after these 8 bits. (8 marks mark for each correct input and output)
2. Use the following circuit, connected to the proper input of the 74HC165, to load the required binary value at power up. When power is first applied, the capacitor is discharged and provides a binary low (binary zero). After a short time period (determined by RC), the capacitor fully charges and provides a binary high (binary one).

Best Practices for Creating Schematics (12 marks):

1. You can use any drawing tool (for example Visio, Altium, Paint, etc).
2. Use a rectangle to represent the shift register.
3. Label the functioname of each pin inside the rectangle.
4. Label the pin numbers outside the rectangle.
5. Group common functions together, for example data inputs, control inputs, outputs, etc. Inputs should be on the left or top/bottom and outputs on the left. Do not place the pins as per the physical construction of the IC.
6. Label all components used for the shift register circuits. The other sections of the block diagram for Part I can be drawn as provided in Figure 8-31.

FIGURE 8-31 Simplified logic diagram of a serial-to parallel converter SRG 8 Serial data in D Control flip-flop CLK GEN in EN Q CLK Data-input register HIGH - 1.7 e -C SC O O O O O O O. O K 100 CLR LOAD SRG 8 CTR DIV 8 Data-output CLR TC register > >C n D D D D Ds Dg Do Dn. C 2 Parallel data out 10 One-shot TC.CLK FIGURE 8-31 Simplified logic diagram of a serial-to parallel converter SRG 8 Serial data in D Control flip-flop CLK GEN in EN Q CLK Data-input register HIGH - 1.7 e -C SC O O O O O O O. O K 100 CLR LOAD SRG 8 CTR DIV 8 Data-output CLR TC register > >C n D D D D Ds Dg Do Dn. C 2 Parallel data out 10 One-shot TC.CLK