use quartus ii and exceute it... i need scrrenshot or picture

library IEEE; use IEEE.STD LOGIC_1164.ALL; a Entity declaration entity encoder4t02 is Port ( input, inputl, input2, input3: in STD_LOGIC; input signals outputO, Outputl: out STD_LOGIC) ; output signals end encoder4t02; Architecture declaration architecture Behavioral of encoder4t02 is begin Process declaration process (input, inputl, input2, input3) begin output Outputl Default value for output Default value for Outputl Ifelse statement to map inputs to Outputs if (input = '1 ) then output0 outputl elsif (inputl = then output0 outputl elsif (input2 = '1 ) then Output outputl ' etsif (input3 = ' 1 i) then output '1 , outputl end if; end process; end Behavioral; library IEEE; use IEEE.STD LOGIC_1164.ALL; a Entity declaration entity encoder4t02 is Port ( input, inputl, input2, input3: in STD_LOGIC; input signals outputO, Outputl: out STD_LOGIC) ; output signals end encoder4t02; Architecture declaration architecture Behavioral of encoder4t02 is begin Process declaration process (input, inputl, input2, input3) begin output Outputl Default value for output Default value for Outputl Ifelse statement to map inputs to Outputs if (input = '1 ) then output0 outputl elsif (inputl = then output0 outputl elsif (input2 = '1 ) then Output outputl ' etsif (input3 = ' 1 i) then output '1 , outputl end if; end process; end Behavioral;