Use the following chart to show the state of a 4 location, 2-way associative cache, that uses LRU. If a location has a number printed in it, the address is valid, if no number appears the contents are invalid. For simplify, the computer only has 16 locations in memory. If the cache takes 5ns to access and RAM takes 60ns, what is the effective time given the sequence?

Time	0	1	2	3	4	5	6	7	8	9	10
Lookup address	-	2	5	6	B	5	2	2	B	C	5
Cache location 00	A
Cache location 01	B
Cache location 10
Cache location11

(For associative cache, first calculate the index of set, (mem address) Mod (the number of sets), then decide if it is a hit or miss, if it is a miss, the Least Recently Used entry will be replaced.

Self practice:

Assume 00110 and 11011 were the last two addresses to be accessed. The cache size consists of 8 entries. Use the Least Recently Used replacement policy. Cash size is the same as above, consisting of 4 entries.

Address: 10011 00001 00110 01010 01110 11001 00001 11100 10100

Direct mapped cache miss rate:

Do the same thing as in Part A, except for a 4-way set associative cache.