Use the following MOSFET parameters in the remaining questions, when you need to if parameters are not provided in the question: y=0.5 v1/2, 20F=0.6 V, VTON = 0.8 V (enhancement mode), VTO,N = -1 V (depletion mode), V70,p= -0.8 V, K'N=100 uA/V?, K'p=40 uA/V2, Cox = 20 fF/um?. (26 pts.) Implement the following function using a standard static complex CMOS gate with minimum cost. Vpp=2.5 V. F = (A + B).C + (A + B).D E i. (6 pts.) If the process technology for implementing this circuit has un=2up, annotate the W/L ratio for each device on your schematic above, for symmetrical HL and LH timing. Assume minimum W/L ratio is 1, and body bias effects can be ignored. ii. (2 pts.) Describe briefly and qualitatively how the device sizing would change if the body bias effects were included. Use the following MOSFET parameters in the remaining questions, when you need to if parameters are not provided in the question: y=0.5 v1/2, 20F=0.6 V, VTON = 0.8 V (enhancement mode), VTO,N = -1 V (depletion mode), V70,p= -0.8 V, K'N=100 uA/V?, K'p=40 uA/V2, Cox = 20 fF/um?. (26 pts.) Implement the following function using a standard static complex CMOS gate with minimum cost. Vpp=2.5 V. F = (A + B).C + (A + B).D E i. (6 pts.) If the process technology for implementing this circuit has un=2up, annotate the W/L ratio for each device on your schematic above, for symmetrical HL and LH timing. Assume minimum W/L ratio is 1, and body bias effects can be ignored. ii. (2 pts.) Describe briefly and qualitatively how the device sizing would change if the body bias effects were included