1. Using a diagram, illustrate how to properly organize 256KB of ROM made of 64K x 8 chips connected to 8088 microprocessor, knowing that the chips have access time of 600 ns and the processor operates at 5MHz clock rate. The chips are to be placed at address 00000H and PLD is the only available option for decoding. (20 points)
2. Using Separate Decoders methodology, show how to connect an 8086 microprocessor to 128KB of RAM using as many 64K x 8 SRAM chips as needed. (10 point)
3. Using Separate Bank Write Strobe methodology, draw a diagram to show how to connect an 8086 microprocessor to 128KB of RAM starting at address E0000H and using 64K x 4 SRAM chips. (10 point)
4. In your own words, explain why different data banks of ROM sections do not require bank selection using A0, BHE or other signals (10 point)
5. Explain in your own words and using diagrams; how does address row/column multiplexing in DRAM (10 point)

Looking at the diagram below, why is it important to add the latch to IO/M, RD, and WR when it doesnt do any demultiplexing? (10 point)