1. Using a diagram, illustrate how to properly organize 256KB of ROM made of 64K x 8 chips connected to 8088 microprocessor, knowing that the chips have access time of 600 ns and the processor operates at 5MHz clock rate. The chips are to be placed at address 00000H and PLD is the only available option for decoding. (20 points)

7 OE IOM RD WR IO/M RD WR Buffered control bus OE A95 Aless A17/54 AA 373 A, Ais A, ALE G 8088 As A, As AL A, Az '244 AI Buffered address bus A, 233 OE A A A. As A A, A A. ALE G 373 OE Z AD AD 245 A B As B B A B A, B A; B A, B B G DIR AD AD AD AD AD AD DT/R DEN D D. D D. D D. D D. Buffered data bus 7 OE IOM RD WR IO/M RD WR Buffered control bus OE A95 Aless A17/54 AA 373 A, Ais A, ALE G 8088 As A, As AL A, Az '244 AI Buffered address bus A, 233 OE A A A. As A A, A A. ALE G 373 OE Z AD AD 245 A B As B B A B A, B A; B A, B B G DIR AD AD AD AD AD AD DT/R DEN D D. D D. D D. D D. Buffered data bus