Using a table similar to that shown in Figure 3.10, calculate

74 divided by 21 using the hardware described in Figure 3.8. You should show

the contents of each register on each step. Assume both inputs are unsigned 6-bit

integers.

Iteration Quotient Divisor 0000 0000 0000 0000 Step Initial values 1: Rem = Rem - Div 2b: Rem 03 sll 0. 00 = 1 3: Shift Div right 0000 0000 0000 0000 0000 0000 0000 0001 0001 0001 0011 0011 0010 0000 0010 0000 0010 0000 0001 0000 0001 0000 0001 0000 0000 1000 0000 1000 0000 1000 0000 0100 0000 0100 0000 0100 0000 0010 0000 0010 0000 0010 0000 0001 Remainder 0000 0111 1110 0111 0000 0111 0000 0111 0111 0111 0000 0111 0000 0111 1111 1111 0000 0111 0000 0111 0000 0011 0000 0011 0000 0011 0000 0001 0000 0001 0000 0001 FIGURE 3.10 Division example using the algorithm in Figure 3.9. The bit examined to determine the next step is circled in color. Divisor Shift right 64 bits 64-bit ALU Quotient Shift left 32 bits Remainder Write Control test 64 bits FIGURE 3.8 First version of the division hardware. The Divisor register, ALU, and Remainder register are all 64 bits wide, with only the Quotient register being 32 bits. The 32-bit divisor starts in the left half of the Divisor register and is shifted right 1 bit each iteration. The remainder is initialized with the dividend. Control decides when to shift the Divisor and Quotient registers and when to write the new value into the Remainder register. Iteration Quotient Divisor 0000 0000 0000 0000 Step Initial values 1: Rem = Rem - Div 2b: Rem 03 sll 0. 00 = 1 3: Shift Div right 0000 0000 0000 0000 0000 0000 0000 0001 0001 0001 0011 0011 0010 0000 0010 0000 0010 0000 0001 0000 0001 0000 0001 0000 0000 1000 0000 1000 0000 1000 0000 0100 0000 0100 0000 0100 0000 0010 0000 0010 0000 0010 0000 0001 Remainder 0000 0111 1110 0111 0000 0111 0000 0111 0111 0111 0000 0111 0000 0111 1111 1111 0000 0111 0000 0111 0000 0011 0000 0011 0000 0011 0000 0001 0000 0001 0000 0001 FIGURE 3.10 Division example using the algorithm in Figure 3.9. The bit examined to determine the next step is circled in color. Divisor Shift right 64 bits 64-bit ALU Quotient Shift left 32 bits Remainder Write Control test 64 bits FIGURE 3.8 First version of the division hardware. The Divisor register, ALU, and Remainder register are all 64 bits wide, with only the Quotient register being 32 bits. The 32-bit divisor starts in the left half of the Divisor register and is shifted right 1 bit each iteration. The remainder is initialized with the dividend. Control decides when to shift the Divisor and Quotient registers and when to write the new value into the Remainder register