Using behavioral Verilog:

a. Build a positive edge triggered T Flip Flop with a synchronous reset to TFF

b. Build a positive edge triggered T Flip Flop with an asynchronous reset to TFF (Copy and reuse your old code from part a with some modifications)

c. Implement a positive edge triggered D Flip Flop with synchronous reset using the TFF with synchronous reset that you have implemented in previous steps

d. Implement a positive edge triggered D Flip Flop with asynchronous reset using the TFF with asynchronous reset that you have implemented in previous steps (Copy and reuse your old code from part c with some modifications)