Using the full adder circuit truth table below,

(a) Implement the full adder using a PLA.

(b) You can implement a full adder using fewer gates than the PLA. Show a simpler implementation than the PLA, and explain in detail how you arrived at your design.

Sol45:

(a) Implementing the full adder using a PLA: The truth table for the full adder can be mapped onto a PLA (Programmable Logic Array) using the following steps:

1. Determine the number of inputs and outputs for the PLA. In this case, there are 3 inputs (A, B, Cin) and 2 outputs (Sum, Cout).
2. Write the minterms for each output (Sum and Cout) in terms of the inputs (A, B, Cin). A minterm is a product term that evaluates to 1 for only one combination of inputs. For example, the minterm for Sum when A=0, B=0, and Cin=0 is A'B'Cin.
3. Write the minterms for each output in binary form. For example, the minterm for Sum when A=0, B=0, and Cin=0 is 0001 (since A'B'Cin = 000 = 0 and all other minterms are 0).
4. Write the truth table for the PLA using the binary minterms for each output. Each row in the truth table corresponds to a unique combination of inputs and outputs (e.g. when A=0, B=0, Cin=0, Sum=0, Cout=0).
5. Simplify the truth table by grouping together rows with the same output values. This can be done using Karnaugh maps or Boolean algebra.
6. Write the simplified Boolean expressions for each output in terms of the inputs.
7. Implement the Boolean expressions using the available logic gates and interconnections.

The resulting PLA diagram for the full adder is shown below:

(b) Implementing the full adder using fewer gates: One possible implementation of the full adder using fewer gates is to use a half adder and an OR gate. The half adder computes the sum of two bits without considering any carry from a previous addition. The OR gate computes the carry output from the addition of the two bits and any carry input from a previous addition.

The truth table for the half adder is:

A	B	Sum	Cout
0	0	0	0
0	1	1	0
1	0	1	0
1	1	0	1

The truth table for the full adder can be derived by combining the truth table for the half adder with an additional input for the carry input (Cin):

A	B	Cin	Sum	Cout
0	0	0	0	0
0	0	1	1	0
0	1	0	1	0
0	1	1	0	1
1	0	0	1	0
1	0	1	0	1
1	1	0	0	1
1	1	1	1	1

To implement the full adder using a half adder and an OR gate, we can use the following circuit: