Using the given diagram, briefly explain the execution process of the $"$sw $t$1,112(10)($$s$4)"$ instruction. Assume that both the instruction cache and data cache are hits, and consider the operation between cache and MEM as write$-$through, while the operation between MEM and Disk is write$-$back. $($Ignore the pipeline$)($Given: $s$4=1000(10))$