Question: Using the requirements and equipment given please complete 1 - 4 : 1 ) A function table of D Flip Flop containing both present state

Using the requirements and equipment given please complete 1-4:
1)A function table of D Flip Flop containing both present state Q and next state Q+;
2)State table for complete operation (A table contains input x,present states of C/B/A,next states
of C/B/A,output z,and present D Flip Flop inputs D2,D1,and D0);
3)K-maps to obtain Boolean equations of D2,D1,D0and z,and the application of DeMorgans to convert them into NAND gate and AND gate formats;
4)Built a circuit diagram
EQUIPMENT REQUIRED:
Global Specialties Design and Prototyping PB-505A
Wire Leads
1 Logic Probe
27400 TTL quad two input NAND gate integrated circuit chip
17408 TTL quad two input AND integrated circuit chip
17410 TTL triple three input NAND integrated circuit chip
174175 TTL Quad D Flip-Flop
LAB INTRODUCTION:
Design a counter which has one input, x, and four outputs, C,B,A, and z. Output signals C,B, and A are
three D Flip-Flop outputs ( Q_(2),Q_(1) and Q_(0)) which form a three-bit binary number with C as the most significant
bit (MSB) and A as the least significant bit (LSB). This binary number will be displayed as a digit on one of the
7-segment LED displays on the PB-505A Digital Lab. Note that the flip-flop outputs are labeled C, B, A, to
match the inputs of the 7-segment LED display on the PB-505A (as shown in Fig.1).
When x=1 the digit should progress through the sequence 0,1,2,3,4,5, and remain at 5
when it is reached. State transitions should occur on the clock pulse. You should determine when
such transitions will occur (i.e., rising or falling edge of the clock pulse). The output z should equal 1
only when the counter has reached five AND while x=1.
If, at any time, x is changed to a 0, the next digit which appears with the next clock pulse should
be a zero. The input x and the clock should be controlled by a logic switch.
quad The output z should control a logic monitor.
quad All unused states (110,111) should transition to the 000 state on the first clock pulse.
Using the requirements and equipment given please

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