Using the verilog code and 2x1 decoder diagram shown below, write a program for the 4x1 decoder diagram. Use array syntax to declare a set of wires or registers.  module DecoderMod(s, o); // module definition input s; output [0:1] o; not(o[0], s); assign o[1] = s; endmodule module MuxMod(s, d, o); input s; input [0:1] d; output o; wire [0:1] s_decoded, and_out; DecoderMod my_decoder(s, s_decoded); // create instance and(and_out[0], d[0], s_decoded[0]); and(and_out[1], d[1], s_decoded[1]); or(o, and_out[0], and_out[1]); endmodule module TestMod; reg s; reg [0:1] d; wire o; MuxMod my_mux(s, d, o); initial begin $display("Time s d o"); $display("--------------"); $monitor("%04d %b %b %b", $time, s, d, o); end initial begin s = 0; d = 2'b00; #1; s = 0; d = 2'b01; #1; s = 0; d = 2'b10; #1; s = 0; d = 2'b11; #1; s = 1; d = 2'b00; #1; s = 1; d = 2'b01; #1; s = 1; d = 2'b10; #1; s = 1; d = 2'b11; end endmodule 

4x1 diagram:

module DecoderMod (s, o); // module definition input s; output [0:1] o; o0 not (o[0], s); assign o[1] s; endmodule module MuxMod (s, d, o); d1 input s; input [0:1] d; output o; wire [0:1] s_decoded, and_out; DecoderMod my decoder(s, s decoded); II create instance and (and_out[0], d[0], s_decoded[0]); and (and_out [1], d[1], s_decoded[1]); or (o, and out[0], and_ out[1]); endmodule module TestMod; reg s; reg [0:1] d; wire O MuxMod my-mux( s, d, o); initial begin Sdisplay("Time sd o"); Sdisplay("-"); Smonitor("Xo4d Xb %b %b", Stine, s, d, o); end initial begin end endmodule module DecoderMod (s, o); // module definition input s; output [0:1] o; o0 not (o[0], s); assign o[1] s; endmodule module MuxMod (s, d, o); d1 input s; input [0:1] d; output o; wire [0:1] s_decoded, and_out; DecoderMod my decoder(s, s decoded); II create instance and (and_out[0], d[0], s_decoded[0]); and (and_out [1], d[1], s_decoded[1]); or (o, and out[0], and_ out[1]); endmodule module TestMod; reg s; reg [0:1] d; wire O MuxMod my-mux( s, d, o); initial begin Sdisplay("Time sd o"); Sdisplay("-"); Smonitor("Xo4d Xb %b %b", Stine, s, d, o); end initial begin end endmodule