Verilog module:

module test$($output $[1$:$0]$ Q$,$ input x$,$ input clock, input reset$)$;

reg $[1$:$0]$ state;

parameter S$0=2\text{'}$b$00,$ S$1=2\text{'}$b$01,$ S$2=2\text{'}$b$10,$ S$3=2\text{'}$b$11$;

always @ $($posedge clock, negedge reset$)$

if$(!$reset$)$ state$<=$S$0$;

else case$($state$)$

S$0$: if$($x$)$ state$<=$

Select answer

; else state$<=$

Select answer

;