VERILOG PLEASE HELP

Consider a multi-cycle discussed in class that performs either the RTN R A + B + C - D or the RTN R A - B + C + D. Assume the control unit for the data path inputs signals start, mode (clk ans reset not counted), and outputs the data path control signals as well as a done signal when it is done executing each RTN. Do the following:

1) Create a data path to execute the RTNs depending on the value of the mode signal. When mode = 0 the data path executes R A + B + C - D or R A - B + C + D when mode = 1. Use if-else statement to model an 8-bit 2-to-1 MUX. Use a case statement to model a 3-to-1 MUX. Note, if-else and case statements must be within always blocks; (they can also be with in initial blocks, but you dont do this when you are modeling a design). For addition and subtraction operations use the arithmetic operators + and -.

2) Construct a FSD for the control unit. The complex sequential circuit shall operate as follows:

Upon (asynchronous) reset the data path and control unit will initialize. Upon start = 1, the control unit shall compute the requested RTN in four clock cycles according to the value of the mode signal value. The start signal stays at 1 only for two clock signals. You would need to set start = 0 after two clock cycles; you would do this in the tester.v (also see example below). When the controller is done executing the RTN, it sets the done signal to 1 (done = 1). Another computation can start when start becomes 1 again. Note: To simplify, implementation does not require checking for the overflow. You can assume that the values for inputs a, b, c, and d are selected such that the RTNs do not generate an overflow.

3) For the control unit, use a case and if-else statements to model the NSG and OG modules. The OG module shall output the control signals required to control the data path as well as the done signal. Note: You may combine the control signals into a vector. This will simply your code.

4) Combine the data path and control unit modules to create a structural model for the complex sequential circuit. Its input parameters should be reset, clock, start, and mode, and 8-bit inputs a, b, c and d. Its outputs should be the output of the register as an 8-bit result and the done signal. You may put $display within modules (inside the always blocks) to output debugging values.

5) Create a test-bench to validate your design using the following test cases. NOTE: Each time you must use long enough simulation time (e.g., #100) to allow the FSM to complete its long task; the controller would use several clock cycles to compute each RTN. First determine how many clock cycles is required to complete executing an RTN and from that you can determine how much minimum simulation time needed for each test case. It is important that you simulate the FSM long enough, but allowing more time will not alter the final result. The following list just shows the test cases; you would need to enter each test case with adequate simulation time and activating and deactivating the start signal. Also finishing project3 will help you model the controller FSM and how the clock signal (clk) is generated and the asynchronous reset is used to reset the circuit.

a. A = 8h01; B = 8h02; C = 8hFF; D = 8h02; mode = 1b0; b. A = 8hFE; B = 8h01; C = 8h01; D = 8h04; mode = 1b1; c. A = 8h01; B = 8hFF; C = 8hFF; D = 8h02; mode = 1b0; d. A = 8hFE; B = 8h02; C = 8hFF; D = 8h02; mode = 1b1;

The following would be an example of a test case: //test case 1 a = 8h01; b = 8h02; c = 8hFF; d = 8hFE; mode = 1b1; $display(); //enter the format to display start = 1; //start the computation #20 start = 0; //deactivate start soon after the controller starts but before finishing the task #100 //allocated additional simulation time more is better than less; if code is wrong more will not help //test case 2