verilog // Quartus II//cyclone II

The purpose of this project is to design an elevator control circuit. The designed system has the following specifications: - The building with the elevator consists of 11 floors (G,1,2,3,4,5,6,7,8,9, and 10 ). - Each floor has one request switch to request the elevator and one LEDR which is on when the elevator booth passes by or stops in that the floor, the number of the current floor has to saved in a register. - The elevator booth has two seven segments to show the current floor and a four control switches to request the destination floor, the number of the destination floor has to saved in a register. - The user requests the elevator in any level through the switch related to that level. After the booth reaches the required level, the user selects the new destination level through the four control switches. - If two or more request switches are activated at the same time, the priority will always be given to the lowest level number (Level G has the highest priority and 10 has the least). - Only the LEDR in the level where currently the booth exists will be on. The remaining 10 LEDRs will be off. - You will need to use the clock from experiment 8 in order to create enough delay to observe the booth's movement between different levels. Submission Guidelines 1. Students should implement the project using Verilog HDL. Schematic designs are allowed for the top design. 2. Students are allowed to work in teams of two or three and students from different sections CANNOT work in the same team. 3. Each team should be able to show a demo of the working project to their lab engineer/instructor and answer all their questions during specific time that will be announced. 4. Students are expected to answer all the questions about all parts of the project during the discussion. 5. Each team should submit a written report that describes the functionality, inputs, and outputs of each defined module. In addition, you need to describe how the modules are connected together to form the top-level design. Moreover, the report should include snapshots of multiple simulation waveforms that demonstrate the correct functionality of the system in the following scenario: a. The reset switch has to be on to start the system with the booth is located in G floor and LEDR0 is on and the booth's 7 segments show 00 . b. A user at any floor can request the booth by setting on the related request switch. For example, if sw5 is set to 1, the booth's 7 segment will show 05 and LEDR5 will be on and LEDR0 will be off. In order to simplify the work, there will be no need in this step to show the transition of the booth between different floors. c. The next step includes the user selecting the new destination floor through the booth's control switches. If the user wants to go to the 10th floor, for example, then switches 13 , 14,15 , and 16 will be set to 1010. d. After that, the user needs to set the Go sw12 to 1 then0 so that the booth starts moving between the current floor (5) and the destination floor (10). While moving, only the LEDR of the current floor will be on starting with LEDR5 reaching to LEDR 10. Moreover, the booth's 7 segments will change the current floor number starting from 5 and reaching to 10 during the booth's transfer. This concludes a complete transfer for the booth. e. The final step in the transfer is to set sw5 to 0 , and sw11 to 1 to make the 10th floor the new current floor. f. A new transfer can be started either by using the booth's control switch to move from the 10th floor to any other destination, or by externally requesting the booth from a new floor using any request switch. 6. Please make sure to follow these rules when you submit your project: a. Place all of your project files (.v, .vwf, ,bdf and report) in one folder. b. Compress the submission folder into a .zip or rar format. c. The name of the compressed file should be Team_[TeamNumber].rar OR Team_[TeamNumber].zip. For example, if your team number is 4 then your submitted file should be named as Team_4.rar OR Team_4.zip. d. Each team should submit the compressed file through Teams before the deadine. d. No late submission will be accepted under any circumstances. 7. Cheating will not be tolerated and will result in zero grade. - Display Digit 0 Digit I 2n Inper Switches I. L.EDh 12:38 clock.bdf W* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. \% " Copyright (C) 1991-2007 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. "/ (/Hpragma file_not_in_maxplusii_format (header "graphic" (version "1.3")) (pin clock.bsf Done this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. ") j Copyright (C) 1991-2007 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. *) (header "symbol" (version "1.1")) (symbol (rect 1616176112 ) (text "clock" (rect 5034 14) (font counter.v module counter (input clock, output reg[31:0] counter_out); always @ (posedge clock) begin counter_out