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Design a Mealy sequence detector that detects the overlapping, right to left, sequence 0110.
I) Verilog Model Requirement 1. Use an assign statement to enter the SOP expression for z, the output of the OG module. See Example 2.16. 2. Directly describe the FSM from the design info (items a and b above). This is like example 5.10 but does not include output z, which is taken care of in step 1.
II) Verilog Model Requirement: Convert the z-Mealy output in part I to Z-Moore Refer to Figure 5.23 for an example. Hint: Add another FF as a separate always block.
5.10 Output:
Example 2.16. A behavior model of a 1-bit 2-to-1 MUX using an assign statement: module muxlbit ( input s, input x,y, output r )i assign r=S \& xs \& Y; endmodule Example 5.10 A Verilog behavior model for the Mealy sequence recognizer in Example 5.2 that recognizes the overlapping sequence " 101n is presented, where the code consists of two sections as follows: Code section 1: A behavior description for the combined NSG and OG. However, note that a combined code for some larger designs may create synthesizing problems, especially when PLDs with restricted hardware resources are used. The code describes the Mealy FSD. The FSD consists of only three states, labeled A, B, and C. Code section 2: A behavior description of the flip-flops with asynchronous reset capability. Upon reset, the FSM is initialized to its initial state A. HDL Model //A Mealy sequence recognizer that detects the overlapping //sequence "101" //Using binary encoded state labels module mealy_seq 1 input clock, reset, x, output reg z parameter A=2b00,B=2b01,C=2b10; \( \mathrm{~ r e g ~ [ 1 : 0 ] ~ c u r r e n t _ s t a t e , ~ n e x t _} \) //SectionI:Acombinednexts output generator (OG) // unknown etates are ignored alwayBe (*) begin cabex (current_etate) end olao begin next_state =Ai z=0j end z=0; end else begin next_state =C : z=0; erd z=1; end else begin next_state =A;; z=0; end default: begin rext_state =2bxx; z=1bx; end endcase And //Section 2: flip-flops always@ (posedge clock, posedge reset) begin if (reset ==1 ) current_state =A; else current_state = next_state; end endmodule Chronologic VCS simulator copyright 1991-2009 Contains Synopsys proprietary information. Compiler version D-2009.12; Runtime version D-2009.12; 0:10:x=120:x=130:x=140:x=050:50:55:60:70:x=170:75:80:x=190:x=0100:x=0z=0z=1x=0z=1 \$finish called from file "testmealy.v", line 32. $finishatsimulationtime110 FIGURE 5.23 The circuit for the Mealy " 101 sequence recognizer. Also illustrated is the conversion of a Mealy output to a Moore output using a synchronizing flip-flop. Example 2.16. A behavior model of a 1-bit 2-to-1 MUX using an assign statement: module muxlbit ( input s, input x,y, output r )i assign r=S \& xs \& Y; endmodule Example 5.10 A Verilog behavior model for the Mealy sequence recognizer in Example 5.2 that recognizes the overlapping sequence " 101n is presented, where the code consists of two sections as follows: Code section 1: A behavior description for the combined NSG and OG. However, note that a combined code for some larger designs may create synthesizing problems, especially when PLDs with restricted hardware resources are used. The code describes the Mealy FSD. The FSD consists of only three states, labeled A, B, and C. Code section 2: A behavior description of the flip-flops with asynchronous reset capability. Upon reset, the FSM is initialized to its initial state A. HDL Model //A Mealy sequence recognizer that detects the overlapping //sequence "101" //Using binary encoded state labels module mealy_seq 1 input clock, reset, x, output reg z parameter A=2b00,B=2b01,C=2b10; \( \mathrm{~ r e g ~ [ 1 : 0 ] ~ c u r r e n t _ s t a t e , ~ n e x t _} \) //SectionI:Acombinednexts output generator (OG) // unknown etates are ignored alwayBe (*) begin cabex (current_etate) end olao begin next_state =Ai z=0j end z=0; end else begin next_state =C : z=0; erd z=1; end else begin next_state =A;; z=0; end default: begin rext_state =2bxx; z=1bx; end endcase And //Section 2: flip-flops always@ (posedge clock, posedge reset) begin if (reset ==1 ) current_state =A; else current_state = next_state; end endmodule Chronologic VCS simulator copyright 1991-2009 Contains Synopsys proprietary information. Compiler version D-2009.12; Runtime version D-2009.12; 0:10:x=120:x=130:x=140:x=050:50:55:60:70:x=170:75:80:x=190:x=0100:x=0z=0z=1x=0z=1 \$finish called from file "testmealy.v", line 32. $finishatsimulationtime110 FIGURE 5.23 The circuit for the Mealy " 101 sequence recognizer. Also illustrated is the conversion of a Mealy output to a Moore output using a synchronizing flip-flop
