Verilog: shifter.v

//32-bit shifter //To get all scores, you cannot use shift operators in this module. module shifter(input [31:0] x, input [4:0] c, input [1:0] op, output reg [31:0] y); //write your code here endmodule

Shifter Implement a 32-bit shifter Input: x (32 bits), c (5 bits), and op (2 bits) Output: y Shifter Implement a 32-bit shifter Input: x (32 bits), c (5 bits), and op (2 bits) Output: y