VHDL codes for AeqB ,AgtB and AltB

= Arithmetic Comparison Design A comparator compares the relative sizes of two numbers. Consider a comparator that has two 6-bit inputs, A and B, which represent unsigned binary. It produces three outputs: AeqB which is set to 1 if A = B. (should be design using ONLY MUX). AgtB which is set to 1 if A > B. (is equal to AeqB + AltB). AltB which is set to 1 if A