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W2: In the RCA 1802 architecture, when an interrupt occurs: 1. The X and P register values are saved in the T register, 2. X

W2: In the RCA 1802 architecture, when an interrupt occurs: 1. The X and P register values are saved in the T register, 2. X is set to 2 and P is set to 1, 3. Interrupts are disabled, 4. Then a fetch is initiated. What instruction should be first in the OS handler?

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