want a verilog code to design the hardware to implement the following function without using shifting, multiplication operators :E$=$A$2$i$+$B$\backslash$times $2$jF$=$E$\backslash$times CWhere:A$,$ B$,$ C and E are $8-$bit unsigned numbersi and j are $3-$bit unsigned numbers.F is $16-$bit unsigned numberDesign SpecificationUse your own choice of multiplier algorithm to implement the multiplier.