We have the following equations describing a circuit with four binary input a, b, c, d and three binary outputs out1, out2, and out3:

1. Study the circuit described by the equations above and write a truth table to describe the behavior.
2. Write a Verilog module called replicator to implement the circuit described by the expressions above.
3. Write a test bench to fully test the replicator module created in step 2.
4. Simulate the circuit using ISim and analyze the resulting waveform in comparison to the truth table from step 1
5. Take full screenshots of the source code of replicator module, the test bench Verilog file, and resulting simulation waveforms to be included in the lab report. Include your analysis of the resulting waveform to explain in details how you can tell whether your Verilog implementation in Step 2 for the circuit is accurate.

out2 = ac + bd out3 = (a + c)(b + d) out1 = out2 + out3 out2 = ac + bd out3 = (a + c)(b + d) out1 = out2 + out3