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We have the following program segment executed on a three - stage ( I , E , and D ) RISC pipeline. The pipeline allows

We have the following program segment executed on a three-stage
(I, E, and D) RISC pipeline. The pipeline allows two simultaneous memory accesses.
100LOAD R1, X #Load from Address X
101 LOAD R2, Y #Load from Address Y
102 INC R1 #Increment R1
103 DEC R2 #Decrement R2
104 BRANCH 107 #Branch to Address 107
105 ADD R1,5 #Add 5 to R1
106 SUB R2,2 #Subtract 2 from R2
107 STORE R2,Z #Store R2 at Address Z
Using delayed branch in pipeline operation in the above program, draw the pipeline timing diagrams:
i-using NOOPS
ii. After rearranging the instructions (optimized delayed branch),
Calculate the number of clock cycles required to execute the above program in each case.

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