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We have the following program segment executed on a three - stage ( I , E , and D ) RISC pipeline. The pipeline allows
We have the following program segment executed on a threestage
I E and D RISC pipeline. The pipeline allows two simultaneous memory accesses.
LOAD R X #Load from Address X
LOAD R Y #Load from Address Y
INC R #Increment R
DEC R #Decrement R
BRANCH #Branch to Address
ADD R #Add to R
SUB R #Subtract from R
STORE RZ #Store R at Address Z
Using delayed branch in pipeline operation in the above program, draw the pipeline timing diagrams:
iusing NOOPS
ii After rearranging the instructions optimized delayed branch
Calculate the number of clock cycles required to execute the above program in each case.
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