Question
we utilized a function generator to provide a clock signal to the flip-flops. Your laboratory kit includes an IC capable of doing this as well.
we utilized a function generator to provide a clock signal to the flip-flops. Your laboratory kit includes an IC capable of doing this as well. Unfortunately, its not included in the Multisim library. The part is CD4541B, a CMOS Programmable Timer. The timer is designed to provide clock signals in the frequency range of DC to 100 kHz. The oscillator is programmed using three external components RTC, CTC, and RS. A copy of the parts data sheet is provided with this problem set. Please read through the data sheet before attempting this problem. 1. (6 points) Using only the resistors and ceramic capacitors provided in your lab kit, choose RTC and CTC to achieve a frequency of approximately 1.61 kHz. Support your choice using the design calculation provided in the part datasheet. Once you have selected RTC, choose RS from the resistors available in your lab kit. Again, support your choice using the design calculation provided in the part datasheet. 2. (9 points) (a) Determine the appropriate logic level on pin 10 to generate a continuous-square wave using the recycle mode. (b) Determine the appropriate logic levels on pins 5 and 6 to enable the auto reset feature and turn off the master reset. (c) Determine the appropriate logic level on pin 9 so that the output is initially low after reset. (d) Determine the appropriate logic levels on pins 12 and 13 so that the frequency of the clock signal available on pin 8 is approximately 0.2 Hz. This will be the operating frequency for your state machine flip-flops during your project demonstration. 3. (4 points) Draw a circuit diagram of the CD4541 implementing all the logic and the component value choices made in the previous parts. Your schematic should show the ICs connections to VDD = 5V and VSS = 0V You can use VDD and VSS for logic 1 and zero as well as power. Please label your external components with their name and value, for example RTC, 10 k . 4. (1 points) Determine the appropriate logic levels on pins 12 and 13 so that the frequency of the clock signal available on pin 8 is approximately 1.6 Hz. You may find this clock frequency useful during the debugging phase of your project.
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