We want to design a trojan activation circuit. Trojans are HW modules inserted into chips during manufacturing. They remain dormant till they receive some activation input through a covert channel. Once activated, they do some harm to the chip. Our trojan activation circuit monitors a serial data line (Sdata) looking for the activation codes, once it detects the activation code, it asserts an output signal (4) that activate the trojan. The activation codes are as follows (the exact order with the specified timing): 1) 1st receiving a 1101_1011 consecutive (i.e. these exact bits in this order) pattern, then 2) Receiving an 0011_0011 pattern within 5,000 cycles from receiving the 1st pattern, then 3) Receiving an 1111_1111 pattern within 1,000 cycles from receiving the 2nd pattern If the codes received violate the timings (e.g. more than 5,000 cycles elapse after the 1st pattern or more than 1,000 cycles elapse before receiving the 3rd pattern), the circuit goes back to waiting for the codes in the proper order and timing (as if no pattern has been received yet). Obtain the required Datapath Show the ASM chart for this circuit Sdata A