What will be Tb (test bench) of this verilog program ??

? . File Edit View Tools Wind | In# 1 module pwm(elk, rat.d cy,clk out, count_value) : 3 input clk, rst: 4 input 12:01d cy: 5 output clk out, count_value: 7 reg clk out, count value: 8 regtis:01 count: 9 reg Elag 10 11 always &(posedge clk or negedge rst) 12 13 begin 14 if (rat) 15 begirn 16 count