When specifiying a data forwarding path ("from where to where") be sure the source of the path is a field in a pipeline register (ex: ID/EX.NPC) and the destination is a specific input of a piece of hardware (ex: the lower input of the ALU in the EX stage) 1. Consider this code, which has a RAW hazard that can be resolved without stalling using data forwarding: DADDU R6, R1, RO DADDUI R6 , R6 , #1 a) What data forwarding hardware must be added to the variation 1 MIPS to handle this code without stalling? Show the required hardware by drawing it in a different color on a diagram of the variation 1 MIPS pipeline. (You do not have to include all the details of the standard pipeline, but give enough that we can see clearly how the new hardware fits in.) The data is being forwarded from where to where? Also, what Boolean expression can be used to decide whether to activate the path that forwards the data in a given clock cycle? b) Suppose the code is changed to insert the instruction shown in the middle: DADDU R6, R1, RO DSUBU R1, R0, R2 DADDUI R6 , R6, #1 How does the data forwarding path change? (Data is forwarded from where to where, with what Boolean expression used to decide to use the path?) c) Suppose the middle instruction is changed to DADDU R6, R1, RO DADDUl R6, R6, #1 DADDUI R6 , R6 , #1 Now, fully describe any data forwarding paths and Boolean expressions needed. How are they the same or different than what you needed in parts a and b? (Note that in a real processor you need Boolean expressions that turn on the right paths for every possible combination of instructions that might be in the pipeline.) When specifiying a data forwarding path ("from where to where") be sure the source of the path is a field in a pipeline register (ex: ID/EX.NPC) and the destination is a specific input of a piece of hardware (ex: the lower input of the ALU in the EX stage) 1. Consider this code, which has a RAW hazard that can be resolved without stalling using data forwarding: DADDU R6, R1, RO DADDUI R6 , R6 , #1 a) What data forwarding hardware must be added to the variation 1 MIPS to handle this code without stalling? Show the required hardware by drawing it in a different color on a diagram of the variation 1 MIPS pipeline. (You do not have to include all the details of the standard pipeline, but give enough that we can see clearly how the new hardware fits in.) The data is being forwarded from where to where? Also, what Boolean expression can be used to decide whether to activate the path that forwards the data in a given clock cycle? b) Suppose the code is changed to insert the instruction shown in the middle: DADDU R6, R1, RO DSUBU R1, R0, R2 DADDUI R6 , R6, #1 How does the data forwarding path change? (Data is forwarded from where to where, with what Boolean expression used to decide to use the path?) c) Suppose the middle instruction is changed to DADDU R6, R1, RO DADDUl R6, R6, #1 DADDUI R6 , R6 , #1 Now, fully describe any data forwarding paths and Boolean expressions needed. How are they the same or different than what you needed in parts a and b? (Note that in a real processor you need Boolean expressions that turn on the right paths for every possible combination of instructions that might be in the pipeline.)
