Which of the following is true for the above 2 verilog codes?

Gate design level is used in the code. 2x1 Multiplexer is designed in the code. All nets in the codes must be defined in the testbench section. Your answer:

A. I,II,III B. I,II C. I,III D. II,III

'timescale lns / Ips module mux (input Io, il, slct, output out); wire slct_n; wire out_1; wire out_2; not (slct_n, slct); and (out_1, 10, slct_n); and (out_2, Il, slct); or (out, out_1, out_2); endmodule timescale ins / Ips module testbench(); reg 10, 11, slct; wire out; integer i; mux dt (.10 (10), Il(11), .slct (slct), .out (out)); initial begin 10=0; Il=0; slct=0; Smonitor ("slct=30b 10=30b Il=0b out=0b", slct, 10, 11, out); for (i=0; i