Which of the following is true for the above verilog code?

A register must be added to the code for the input.
	Output is equal to the inverse of the input.
	Initial block can also be used instead of always block.
	A register must be added to the code for the output.

"timescale Ins/ lps module flipflop (Q, D, clk); input D, clk; output Q; always (posedge clk) begin Q