With schematic diagrams, explain each of the following cache memory architecture: 1. Direct Mapped 2. Set Associative 3. Fully Associative For the following memory access operations of the same index, determine Hit/Miss and Way numbers for a 4-way set associative cache memory when (1) LRU and (2) FIFO replacement techniques are used. Memory access [100] Memory access [200] Memory access [300] Memory access [200] Memory access [400] Memory access [100] Memory access [500]