Write a behavioral Verilog code describing the figure of a restoring divider from restoring division algorithm.

b[15:00] clk reg b sub So mux reg al31:00] 130:00] mux reg q r15:00] 31:00] b[15:00] clk reg b sub So mux reg al31:00] 130:00] mux reg q r15:00] 31:00]