Write a behavioral verilog module 2mux2in4b and a test bench 2mux2in4b_tb for a 2-input, 4-bit MUX with data input vectors D0 and D1, and an output vector Y and index them from 1 to 4. For each value of the function inputs, the test bench shouldd check that the output is correct for all combinations of data-input calues and display an error message if it is incorrect.

Truth table for a 2 input 4 bit MUX

Inputs		Outputs
G	S	1Y	2Y	3Y	4Y
1	x	0	0	0	0
0	0	1D0	2D0	3D0	4D0
0	1	1D1	2D1	3D1	4D1