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Write a System Verilog file for the finite state machine given below. a . Use the Quartus Prime Lite software to create the file. Include

Write a System Verilog file for the finite state machine given below.
a. Use the Quartus Prime Lite software to create the file. Include the text in your
homework.
b. Simulate the file in Modelsim. Get a screen shot of your Modelsim simulation
and include it in the homework.
c. Include your sv file with your homework file submission.
Z = Q2
D2= Q1 Q0 X
D1= Q2 X'+ Q1 Q0' X'+ Q1' Q0 X'
D0= Q1 Q0'+ Q1' X
Input Outputs
State Name Q2 Q1 Q0 X State Name Q2(t+1) Q1(t+1) Q0(t+1) Z D2 D1 D0
A 0000 A 0000000
A 0001 B 0010001
B 0010 C 0100010
B 0011 B 0010001
C 0100 D 0110011
C 0101 B 0010001
D 0110 A 0000000
D 0111 E 1000100
E 1000 C 0101010
E 1001 B 0011001
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