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Write a System Verilog file for the finite state machine given below. a . Use the Quartus Prime Lite software to create the file. Include
Write a System Verilog file for the finite state machine given below.
a Use the Quartus Prime Lite software to create the file. Include the text in your
homework.
b Simulate the file in Modelsim. Get a screen shot of your Modelsim simulation
and include it in the homework.
c Include your sv file with your homework file submission.
Z Q
D Q Q X
D Q X Q Q X Q Q X
D Q Q Q X
Input Outputs
State Name Q Q Q X State Name Qt Qt Qt Z D D D
A A
A B
B C
B B
C D
C B
D A
D E
E C
E B
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