write a verilog code to implement the following function without using $>>,<<,+,*,\backslash$ operators:

E $=$ A $/2^$i$+$ B $*2^$j

F $=$ E $*$ C

Where:

$$ A$,$ B$,$ C and E are $8-$bit unsigned numbers

$$ i and j are $3-$bit unsigned numbers.

$$ F is $16-$bit unsigned number

Design Specification:

$$ Implement the design using Verilog language. Do not use the following math operations:

$-,+,*,/,<<,>>$ shift$/$rotate$.$ You need to implement them yourself.

$$ The top design name is mydesign and the port definition is illustrated below. You must

use the below testbench and template in your design.

$$ Use your own choice of multiplier algorithm to implement the multiplier

$`$timescale $1$ns$/100$ps

module mydesign$\_$tb;

reg $[7$:$0]$ A;

reg $[7$:$0]$ B;

reg $[7$:$0]$ C;

reg $[2$:$0]$ i$,$ j;

wire $[15$:$0]$ F;

$//$ Mydesign one round in hardware

mydesign mydesign $($

$.$A $($A$),$

$.$B $($B$),$

$.$C $($C$),$

$.$i $($i$),$

$.$j $($j$),$

$.$F $($F$)$

$)$;

initial begin

$monitor $("($values are in HEX$)$ A$=\%$h B$=\%$h C$=\%$h i$=\%$h j$=\%$h F$=\%$h$",$ A$,$ B$,$ C$,$

i$,$ j$,$ F$)$;

A$=8\text{'}$h$06$; B$=8\text{'}$h$06$; C$=8\text{'}$h$06$ ; i$=3\text{'}$h$1$; j$=3\text{'}$h$1$;

#$10$;

A$=8\text{'}$h$01$; B$=8\text{'}$h$01$; C$=8\text{'}$h$01$ ; i$=3\text{'}$h$1$; j$=3\text{'}$h$1$;

#$10$;

A$=8\text{'}$hFF; B$=8\text{'}$hFF; C$=8\text{'}$hFF ; i$=3\text{'}$h$7$; j$=3\text{'}$h$7$;

#$10$;

A$=8\text{'}$hFF; B$=8\text{'}$hFF; C$=8\text{'}$hFF ; i$=3\text{'}$h$0$; j$=3\text{'}$h$0$;

#$10$;

$stop;

end

endmodule

write a verilog code to implement the following function without using $>>,<<,*,/$:

E $=$ A $/2^$i$+$ B$^$j

F $=$ E $*$C

Where:

$$ A$,$ B$,$ C and E are $8-$bit unsigned numbers

$$ i and j are $3-$bit unsigned numbers.

$$ F is $16-$bit unsigned number

Design Specification:

$$ Implement the design using Verilog language. Do not use the following math operations:

$-,+,,/,$ shift$/$rotate$.$ You need to implement them yourself.

$$ The top design name is mydesign and the port definition is illustrated below. You must

use the below testbench and template in your design.

$$ Use your own choice of multiplier algorithm to implement the multiplier

timescale $1$ns$/100$ps

module mydesign$\_$tb;

reg $[7$:$0]$ A;

reg $[7$:$0]$ B;

reg $[7$:$0]$ C;

reg $[2$:$0]$ i$,$ j;

wire $[15$:$0]$ F;

$//$ Mydesign one round in hardware

mydesign mydesign $($

$.$A $($A$),$

$.$B $($B$),$

$.$C $($C$),$

$.$i $($i$),$

$.$j $($j$),$

$.$F $($F$)$

$)$;

initial begin

$monitor $("($values are in HEX$)$ A$=\%$h B$=\%$h C$=\%$h i$=\%$h j$=\%$h F$=\%$h$",$ A$,$ B$,$ C$,$

i$,$ j$,$ F$)$;

A$=8\text{'}$h$06$; B$=8\text{'}$h$06$; C$=8\text{'}$h$06$ ; i$=3\text{'}$h$1$; j$=3\text{'}$h$1$;

#$10$;

A$=8\text{'}$h$01$; B$=8\text{'}$h$01$; C$=8\text{'}$h$01$ ; i$=3\text{'}$h$1$; j$=3\text{'}$h$1$;

#$10$;

A$=8\text{'}$hFF; B$=8\text{'}$hFF; C$=8\text{'}$hFF ; i$=3\text{'}$h$7$; j$=3\text{'}$h$7$;

#$10$;

A$=8\text{'}$hFF; B$=8\text{'}$hFF; C$=8\text{'}$hFF ; i$=3\text{'}$h$0$; j$=3\text{'}$h$0$;

#$10$;

$stop;

end

endmodule