1. Write a Verilog module called myAnd to implement the logic AND gate.
2. Write a test bench to test the myAnd module created in step 3. Simulate the circuit using ISim and analyze the resulting waveform.
3. Take full screenshots of the source code of myAnd module, the test bench Verilog file, and resulting simulation waveforms to be included in the lab report. Also include your waveform analysis in the lab report.