Write a Verilog program on this 4x1 Multiplexer USING arrays and modules.

The output must look like this.

S1 S 0 4x1 MUX 00 01 02 o3 do d 2 d 3 4. m4xlarray.v outputs: Time 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 12 13 01 01 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 18 19 21 23 25 01 01 01 01 01 01 30 32 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 34 35 36 37 38 39 10 10 10 45 48 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 50 51 52 53 54 56 57 58 59 60 61 62 63