Write a Verilog program that simulates the outputs of gray-code-to-binary-code converter. First write a module named GBC which takes w, x, y, z as inputs and a, b, c, d as outputs. Then write a test bench module named bcd_tb to test the GBC module. Compile and run your program and show the outputs for all 16 combinations of w, x, y, z. (please use comments to explain code)