Write a VHDL file (block_d.vhd) with the dataflow description of block_d.

A car manufacturer is to incorporate a driver fatigue detection system based on the frequency and duration of blinks.

The system consists of the following elements:

1.An oscillator generating a 200 ms period clock signal, clk.

2.A reset signal, rst, active at high level for 300 ms when the car is started.

3.An infrared camera that analyzes the driver's eyes. It has an output, blink_in, which provides a '1' if it detects closed eyes and a '0' otherwise. This signal is synchronous with clk.

4.A visual alarm on the dashboard recommending the driver to rest, and it is triggered by the signal fatigue_out.

5.A loud audible alarm triggered by signal danger_out.

6.An FPGA that receives clk, rst and blink_in and generates fatigue_out and danger_out

Structure of the system like this:

All input signals (blink_in, clk y rst), outputs (fatigue_out y danger_out) and internal signals (thirty_s y sleep_s) are 1-bit signals, except signal accum_s which is a 12-bits bus. The system is divided into four blocks, which are detailed below.

Block_d is a combinational circuit and it is responsible for generating signals fatigue_out and danger_out according to the following specifications:

- Danger_out must activate if the driver's eyes are closed continously for more than 700 milliseconds or if the accumulated time with the eyes closed during a 15 seconds period exceeds 5 seconds (25 cycles of the clock signal, clk).

- Fatigue_out must activate if the accumulated time with the eyes closed during a 15 seconds period is between 2 and 5 seconds (10 and 25 cycles of the clock signal, clk, respectively).

The following schematic, with the signal names according to the entity description

Each interconnection marked with an oblique line represents a 12-bits bus, the rest are one bit signals. The numbers in the schematic are in base 10

Write a VHDL file (block_d.vhd) with the dataflow description of block_d. It must have the following entity declaration:

entity block_d is Port ( sleep_in : in STD_LOGIC; accum_in : in STD_LOGIC_VECTOR (11 downto 0); danger_out : out STD_LOGIC; fatigue_out : out STD_LOGIC); end block_d;

fifteen_s block_a accum_s -fatigue_out block_b 12 sleep_s block_d T clk rst danger_out 4 clk rst block_c blink_in clk clk rst sleep_in accum_in danger_out > 25 fatigue_out 10 IV