write an instantiation for this verilog code$($calling in main$)$ module Add$\_16($

input $[15$:$0]$ A$,$

input $[15$:$0]$ B$,$

input C$,$

output $[15$:$0]$ Sum,

output Cout

$)$;

wire $[15$:$0]$ T;

assign T$[0]=$ C;

FullAdder FA$0(.$A$($A$[0]),.$B$($B$[0]),.$Cin$($T$[0]),.$Sum$($Sum$[0]),.$Cout$($T$[1]))$;

FullAdder FA$1(.$A$($A$[1]),.$B$($B$[1]),.$Cin$($T$[1]),.$Sum$($Sum$[1]),.$Cout$($T$[2]))$;

FullAdder FA$2(.$A$($A$[2]),.$B$($B$[2]),.$Cin$($T$[2]),.$Sum$($Sum$[2]),.$Cout$($T$[3]))$;

FullAdder FA$3(.$A$($A$[3]),.$B$($B$[3]),.$Cin$($T$[3]),.$Sum$($Sum$[3]),.$Cout$($T$[4]))$;

FullAdder FA$4(.$A$($A$[4]),.$B$($B$[4]),.$Cin$($T$[4]),.$Sum$($Sum$[4]),.$Cout$($T$[5]))$;

FullAdder FA$5(.$A$($A$[5]),.$B$($B$[5]),.$Cin$($T$[5]),.$Sum$($Sum$[5]),.$Cout$($T$[6]))$;

FullAdder FA$6(.$A$($A$[6]),.$B$($B$[6]),.$Cin$($T$[6]),.$Sum$($Sum$[6]),.$Cout$($T$[7]))$;

FullAdder FA$7(.$A$($A$[7]),.$B$($B$[7]),.$Cin$($T$[7]),.$Sum$($Sum$[7]),.$Cout$($T$[8]))$;

Ful...

module FullAdder $($A$,$B$,$Cin,Sum, Cout$)$;

input A;

input B;

input Cin;

output Sum;

output Cout;

assign Sum$=($A$^$B$^$Cin$)$;

assign Cout $=(($A&B$)|($B&Cin$)|($A&Cin$))$;

endmodule

module shift$\_$left$($

input $[7$:$0]$ B$,$

input $[2$:$0]$ j$,$

output reg $[7$:$0]$ result

$)$;

integer k;

always @$*$ begin

$//$ Shift A to the left by i bits

result $=8\text{'}$b$0$;

for $($k $=0$; k $<8$; k $=$ k $+1)$ begin

if $(($k $+$ j$)<8)$

result$[$k $+$ j$]=$ B$[$k$]$;

end

end

endmodule

module shift$\_$right $($A $,$ i $,$ R $)$;

input $[7$:$0]$A;

input $[3$:$0]$i;

output reg $[7$:$0]$R;

always @$($A or i$)$

begin

case $($i$)$

$3\text{'}$b$000$: R $<=$ A;

$3\text{'}$b$001$: R $<=\{1\text{'}$b$0,$A$[7$:$1]\}$;

$3\text{'}$b$010$: R $<=\{2\text{'}$b$0,$A$[7$:$2]\}$;

$3\text{'}$b$011$: R $<=\{3\text{'}$b$0,$A$[7$:$3]\}$;

$3\text{'}$b$100$: R $<=\{4\text{'}$b$0,$A$[7$:$4]\}$;

$3\text{'}$b$101$: R $<=\{5\text{'}$b$0,$A$[7$:$5]\}$;

$3\text{'}$b$110$: R $<=\{6\text{'}$b$0,$A$[7$:$6]\}$;

$3\text{'}$b$111$: R $<=\{7\text{'}$b$0,$A$[7]\}$;

endcase

end

endmodule

module Multiplier $($a$,$b$,$p$)$;

input $[7$:$0]$ a$,$b;

wire $[15$:$0]$ m$0,$m$1,$m$2,$m$3,$m$4,$m$5,$m$6,$m$7$;

wire $[15$:$0]$ s$1,$s$2,$s$3,$s$4,$s$5,$s$6,$s$7$;

output $[15$:$0]$ p;

wire $[7$:$0]$C;

assign m$0=\{1\text{'}$b$0,\{8\{$a$[0]\}\}\}$ & b$[7$:$0]$;

assign m$1=\{1\text{'}$b$0,\{8\{$a$[1]\}\}\}$ & b$[7$:$0]$;

assign m$2=\{1\text{'}$b$0,\{8\{$a$[2]\}\}\}$ & b$[7$:$0]$;

assign m$3=\{1\text{'}$b$0,\{8\{$a$[3]\}\}\}$ & b$[7$:$0]$;

assign m$4=\{1\text{'}$b$0,\{8\{$a$[4]\}\}\}$ & b$[7$:$0]$;

assign m$5=\{1\text{'}$b$0,\{8\{$a$[5]\}\}\}$ & b$[7$:$0]$;

assign m$6=\{1\text{'}$b$0,\{8\{$a$[6]\}\}\}$ & b$[7$:$0]$;

assign m$7=\{1\text{'}$b$0,\{8\{$a$[7]\}\}\}$ & b$[7$:$0]$;

Add$\_16$ ad$0($ m$0,\{$m$1,1\text{'}$b$0\},1\text{'}$b$0,$ s$1,$ C$[0])$;

Add$\_16$ ad$1($ s$1,\{$m$2,\{2\{1\text{'}$b$0\}\}\},$ C$[0],$ s$2,$ C$[1])$;

Add$\_16$ ad$2($ s$2,\{$m$3,\{3\{1\text{'}$b$0\}\}\},$ C$[1],$ s$3,$ C$[2])$;

Add$\_16$ ad$3($ s$3,\{$m$4,\{4\{1\text{'}$b$0\}\}\},$ C$[2],$ s$4,$ C$[3])$;

Add$\_16$ ad$4($ s$4,\{$m$5,\{5\{1\text{'}$b$0\}\}\},$ C$[3],$ s$5,$ C$[4])$;

Add$\_16$ ad$5($ s$5,\{$m$6,\{6\{1\text{'}$b$0\}\}\},$ C$[4],$ s$6,$ C$[5])$;

Add$\_16$ ad$6($ s$6,\{$m$7,\{7\{1\text{'}$b$0\}\}\},$ C$[5],$ s$7,$ C$[6])$;

assign p$=$s$7$;

endmodule

module FullAdder$8$Bits$($

input $[7$:$0]$ A$,$

input $[7$:$0]$ B$,$

input C$,$

output $[7$:$0]$ Sum,

output Cout

$)$;

wire $[7$:$0]$ T;

assign T$[0]=$ C;

FullAdder FA$0(.$A$($A$[0]),.$B$($B$[0]),.$Cin$($T$[0]),.$Sum$($Sum$[0]),.$Cout$($T$[1]))$;

FullAdder FA$1(.$A$($A$[1]),.$B$($B$[1]),.$Cin$($T$[1]),.$Sum$($Sum