Write Verilog 2001 code for the following.

Design a 4-bit combinational unsigned integer multiplier based on the parallel architecture (shown below), and write a self-checking Verilog testbench to functionally verify your design. You can use two slices of 4-bit carry-look-ahead adders to make an 8-bit adder. For functional verification, you can use an inferred (by using the Verilog multiplication operator *) 4-bit integer multiplier as the reference model.

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half_adder.v

module half_adder( input A,B, output Y,carry);

assign Y = A^B; assign carry = (A&B); endmodule

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Source Code CLA_adder_top.v

module CLA_adder( input[3:0] A_top, B_top, input Cin, output[3:0] sum, output Cout, );

wire[3:0] P, G; wire[4:0] C;

half_adder U1(.A(A_top[0]), .B(B_top[0]), .Y(P[0]), .carry(G[0])); half_adder U2(.A(A_top[1]), .B(B_top[1]), .Y(P[1]), .carry(G[1])); half_adder U3(.A(A_top[2]), .B(B_top[2]), .Y(P[2]), .carry(G[2])); half_adder U4(.A(A_top[3]), .B(B_top[3]), .Y(P[3]), .carry(G[3]));

assign C[0] = Cin; assign C[1] = G[0]|(P[0]&Cin); assign C[2] = G[1]|(P[1]&G[0])|(P[1]&P[0]&C[0]); assign C[3] = G[2]|(P[2]&G[1])|(P[2]&P[1]&G[0])|(P[2]&P[1]&P[0]&C[0]); assign C[4] = G[3]|(P[3]&G[2])|(P[3]&P[2]&G[1])|(P[3]&P[2]&P[1]&G[0])|(P[3]&P[2]&P[1]&P[0]&C[0]);

assign Cout = C[4]; assign sum[3] = C[3]^P[3]; assign sum[2] = C[2]^P[2]; assign sum[1] = C[1]^P[1]; assign sum[0] = C[0]^P[0];

endmodule

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Parallel Unsigned Integer Multiplier (3 Thus the 4-bit multiplier can be implemented as shown below: Shift and zero padding Shift b3 ne Snift b2 PP2 Shift b1 PPI Note It is combinational! Snift b0 PPO adding Parallel Unsigned Integer Multiplier (3 Thus the 4-bit multiplier can be implemented as shown below: Shift and zero padding Shift b3 ne Snift b2 PP2 Shift b1 PPI Note It is combinational! Snift b0 PPO adding