Y=2

Z=2

(c) Consider a system in which bus cycles takes 5 YZ ns. Transfer of bus control in either direction, from processor to I/O device or vice versa, takes half a bus cycle. One of the I/O devices has a data transfer rate of 5X KB/s and employs DMA. Data is transferred one byte at a time. The system engineer is considering a DMA configuration in either burst mode (where the DMA interface gains bus mastership prior to the start of a block transfer and maintains control of the bus until the whole block is transferred), or in "cycle-stealing mode" (at a transfer rate of 1-byte per cycle). Evaluate the performance difference between the 2 modes using a sample data block of 128 bytes, in terms of the transfer time. (10 marks)