You are asked to design a brand new flip-flop by making use of a single D flip-flop and minimum number of other logic gates. On the rising edge of the clock, the behavior of the new flip-flop is specified in the table below. For all other cases, the circuit just holds the current state. A Q(t + A) 0 0 1 Q(t)' sample_exam2_sol.pdf A Circuit CLOCK Q' (a) [8 Points] Specify the input to D-FF in the table below: A Q(t) D(t) 0 0 0 1 1 0 1 1 (b) [12 Points] Using the excitation table from (a), design the circuit using a 1-bit D flip-flop and minimal number of logic gates