You are given the following data about a virtual memory system: (a)The TLB can hold 1024 entries and can be accessed in 1 clock cycle (1 nsec). (b) A page table entery can be found in 100 clock cycle or 100 nsec. (c) The average page replacement time is 6 mse. If page references are handled by the TLB 99% of the time, and only 0.01% lead to a page fault, What is the effective address translation time ?