You are to design a baby as an fsm. Your baby has three states : Sleeping (also initial), Hungry and Crying. Your baby's interface to the world is via three signals: green, yellow, red. She sets green high when sleeping, yellow high when hungry and red high when crying. She stays in the state crying unless she is fed and returns to sleeping state when fed. a) Draw the block diagram of your baby module b) drive the truth table c) drive the next state and output logic. d) implement your baby in Verilog e) write the test bench and prove that your system is working by simulation