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You are to design a Moore type synchronous Finite State Machine. There is a Reset, a single input X, and a single output Z. The
You are to design a Moore type synchronous Finite State Machine. There is a Reset, a single input X, and a single output Z. The objective of the FSM is to determine when the last three X inputs sampled on the rising clock edges are alternating- that is, are in a sequence 010 or 101. The FSM machine starts monitoring X after the Reset input has dropped. Sequences can overlap, so that 0101 will result in two consecutive outputs of 1. The following example illustrates the desired behaviour, where Reset and X values are shown on each rising clock edge and the desired output Z (note the output Z on the clock cycle after the complete sequence is detected. This is expected for a Moore state machine) 1. Draw a state diagram for this state machine. 2. Complete a state transition table to compute the next state and outputs for this state diagram
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