You are to design a mother as finite state machine. Mother has three inputs green,yellow,red. Mother is initially in birth state then she makes a transition to Content state. She stays in that state as long as the input to the module is green. if not her state changes to observant State. In the observant state if she receives a green input she returns back to the Content state and if not she passes to feeding state. Mother states in the feeding state as long as she recives a green. She has only one output: milk. She sets milk high in the feeding state. a) Draw the block diagram of your baby module b) drive the truth table c) drive the next state and output logic. d) implement your baby in Verilog e) write the test bench and prove that your system is working by simulation