You have been assigned to do an upgrade on the simple $8-$bit microprocessor system we used

as an example at the beginning of the chapter. For the new design you will be using the same

processor, but clocking it at $8MHz$ instead of at $5MHz.$ To reduce the number of packages

on the board, you will be using $27648K8$ EPROMs instead of the $2732$ devices in the old

design. The $2764$ devices have $13$ address inputs, A$0-$A$12,$ and $8$ data outputs, D$0-$D$7.$ The

$2764$ s also have a chip select input, CS#$,$ and an output enable input, OE#$.$ The timing values

for the $2764$ speed$-$grade chosen are $t_{\text{A}\text{C}\text{C}}=250ns,t_{CE}=250ns,$ and $t_{OE}=100ns.$

a$.$ Determine how many $2764$ devices are needed to supply the required $32K$ bytes of

EPROM.

b$.$ Draw a circuit diagram showing the address bus, data bus, and control bus connections to

the required number of devices. $($You can use slash numbered bus lines instead of

individual address and data lines.$)$

c$.$ Construct an address decoder worksheet that shows the address lines connected to each of

the new devices and the address range provided by each.

d$.$ You want to continue to use the $74$LS$138$ EPROM address decoder. Show the

connections you would make to the $74$LS$138$ EPROM address decoder so that it provides

CS# signals to the new devices and gives each the desired address range in the overall

system memory map.

e$.$ According the processor data sheet, the processor has a TCLAV of $60ns,$ a $T_{DVCl}$ of $60ns,$

and a TCLRL of $100ns$ when clocked at $8MHz.$ Use these values and the $2764$ timing

values given above to do an address access, chip select access, and an output enable

access timing loop analysis for the new EPROMs.