You have been designated to design a $32$ KB $4-$ way set associative cache. Each block in the memory is $16$ Bytes. The cache should be Virtually Indexed Physically Tagged type to avoid aliasing. The virtual address is $36$ bits long. The physical address is $32$ bits long. Page offset has the same length $($number of bits$)$ in both the virtual and physical address. We know that the physical page offset is the total number of bits of the byte offset and set index.

a$)$ What is the page size?

b$)$ The characteristics of a $32$ KB $4-$ way set associative $($SA$)$ cache, a $8$KB DM cache, and that of a $32KB4-$way SA Way $-$ Prediction $($Way $-$ P$)$ cache are given in the table below. Use the Average Memory Access Time $($in cycles$)$ to decide if the $32$KB $4-$way SA Way $-$ P cache perform better than the $32$KB $4$way SA$.$

$\backslash$table$[[,32$KB $8-$way SA$,4$KB DM$,\backslash$table$[[32$KB $8-$way SA Way$-],[$P$]]],[$Hit Rate,$92\%,80\%,92\%$